This invention relates to Flash Electrically-Programmable Erasable Read-Only-Memories (Flash EPROMs). In particular, this invention relates to a circuit for programming the floating gates of integrated-circuit memories such as Flash EPROMs.
Flash EPROM memories are generally described in U.S. patent application Ser. No. 08/315,526 filed Sep. 30, 1994, entitled "FLASH EPROM CONTROL WITH EMBEDDED PULSE TIMER AND WITH BUILT-IN SIGNATURE ANALYSIS", also assigned to Texas Instruments Incorporated. That Application is hereby incorporated herein.
In Flash EPROMs designed to operate using either 3 V or 5 V voltage supply, the wordline read voltage is boosted during the 3 V mode of operation. The circuit for boosting the wordline read voltage normally requires a large boost capacitor connected to the wordline supply voltage terminal connected to the wordline-select circuitry. For example, if the chip supply voltage V.sub.CC is 3 V, the boosting circuit may double the 3 V to create a wordline supply voltage of perhaps 5 V during read operation. However, during the programming mode of operation, the same wordline supply voltage terminal must be boosted (pumped) from a low voltage (perhaps 5 V) to high voltage (typically 12 V). Due to the large (perhaps 400 picofarads) boost capacitor BC, required by the low-voltage read operation, the rate of the programming voltage ramp slows the programming time significantly. During the nonlinear ramp of the programming voltage, most of the time is spent in reaching the last twenty to thirty percent of the final twelve volts.
In Flash EPROMs and other devices having a high boost capacitance connected to terminals, there is need for a circuit that decreases the voltage ramp time at the wordline voltage supply terminal and, therefore, improves the speed of operation.